Title:
Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects
Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects
dc.contributor.advisor | Bakir, Muhannad S. | |
dc.contributor.author | Jo, Paul K. | |
dc.contributor.committeeMember | Brand, Oliver | |
dc.contributor.committeeMember | Krishna, Tushar | |
dc.contributor.committeeMember | Cardoso, Adilson | |
dc.contributor.committeeMember | Sitaraman, Suresh | |
dc.contributor.department | Electrical and Computer Engineering | |
dc.date.accessioned | 2020-01-14T14:46:28Z | |
dc.date.available | 2020-01-14T14:46:28Z | |
dc.date.created | 2019-12 | |
dc.date.issued | 2019-10-11 | |
dc.date.submitted | December 2019 | |
dc.date.updated | 2020-01-14T14:46:28Z | |
dc.description.abstract | This research proposes and demonstrate 1) a new compliant interconnect that can provide cost-effective and simple fabrication process and allow high-degree of freedom in design and 2) advanced heterogeneous multi-die integration platform enabled by the new compliant interconnect. Interconnects play a critical role in virtually all microelectronic applications. They are key in influencing microsystem form factor, electrical performance, power consumption, and signal integrity. Of particular importance are first-level interconnects, which are used to electrically interconnect and mechanically bond a die to a package substrate. The density, electrical attributes, and mechanical properties of first-level interconnects impact the overall mechanical integrity, signaling bandwidth density, and power supply noise of microsystems. While solder bumps have become a key technology for first-level interconnects, the technology unfortunately leaves a number of attributes desired in modern microsystems. Compliant interconnects can circumvent many of the challenges in solder bumps as they can compensate for surface non-uniformity on the attaching substrate and CTE mismatch induced warpage and provide non-permanent contact. To this end, novel compliant interconnects for emerging electronic devices and new heterogeneous multi-die integration platform enabled by the compliant interconnects are explored. | |
dc.description.degree | Ph.D. | |
dc.format.mimetype | application/pdf | |
dc.identifier.uri | http://hdl.handle.net/1853/62301 | |
dc.language.iso | en_US | |
dc.publisher | Georgia Institute of Technology | |
dc.subject | Compliant interconnect | |
dc.subject | Heterogeneous integration | |
dc.subject | Package | |
dc.subject | 2.5D | |
dc.subject | 3D | |
dc.subject | System-level integration | |
dc.subject | System-in-package | |
dc.title | Polylithic integration of heterogeneous multi-die enabled by compressible microinterconnects | |
dc.type | Text | |
dc.type.genre | Dissertation | |
dspace.entity.type | Publication | |
local.contributor.advisor | Bakir, Muhannad S. | |
local.contributor.corporatename | School of Electrical and Computer Engineering | |
local.contributor.corporatename | College of Engineering | |
relation.isAdvisorOfPublication | 752d9ed4-97ec-4a80-9920-4b4d3e762de1 | |
relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
thesis.degree.level | Doctoral |