Title:
Compiler Optimizations for Multithreaded Multicore Network Processors

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dc.contributor.advisor Pande, Santosh
dc.contributor.author Zhuang, Xiaotong en_US
dc.contributor.committeeMember Gupta, Rajiv
dc.contributor.committeeMember Lee, Hsien-Hsin Sean
dc.contributor.committeeMember Pu, Calton
dc.contributor.committeeMember Schwan, Karsten
dc.contributor.department Computing en_US
dc.date.accessioned 2006-09-01T19:34:22Z
dc.date.available 2006-09-01T19:34:22Z
dc.date.issued 2006-07-07 en_US
dc.description.abstract Network processors are new types of multithreaded multicore processors geared towards achieving both fast processing speed and flexibility of programming. The architecture of network processors considers many special properties for packet processing, including multiple threads, multiple processor cores on the same chip, special functional units, simplified ISA and simplified pipeline, etc. The architectural peculiarities of network processors raise new challenges for compiler design and optimization. Due to very high clocking speeds, the CPU memory gap on such processors is huge, making registers extremely precious. Moreover, the register file is split into two banks, and for any ALU instruction, the two source operands must come from different banks. We present and compare three different approaches to do register allocation and bank assignment. We also address the problem of sharing registers across threads in order to maximize the utilization of hardware resources. The context switches on the IXP network processor only happen when long latency operations are encountered. As a result, context switches are highly frequent. Therefore, the designer of the IXP network processor decided to make context switches extremely lightweight, i.e. only the program counter(PC) is stored together with the context. Since registers are not saved and restored during context switches, it becomes difficult to share registers across threads. For a conventional processor, each thread can assume that it can use the entire register file, because registers are always part of the context. However, with lightweight context switch, each thread must take a separate piece of the register file, making register usage inefficient. Programs executing on network processors typically have runtime constraints. Scheduling of multiple programs sharing a CPU must be orchestrated by the OS and the hardware using certain sharing policies. Real time applications demand a real time aware OS kernel to meet their specified deadlines. However, due to stringent performance requirements on network processors, neither OS nor hardware mechanisms is typically feasible. In this work, we demonstrate that a compiler approach could achieve some of the OS scheduling and real time scheduling functionalities without introducing a hefty overhead. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 865736 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/11566
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Runtime constraints en_US
dc.subject Register allocation
dc.subject Compiler optimization
dc.subject Multitheading
dc.subject Multicore
dc.subject Network processors
dc.subject.lcsh Registers (Computers) en_US
dc.subject.lcsh Packet switching (Data transmission) en_US
dc.subject.lcsh High performance processors en_US
dc.subject.lcsh Compilers (Computer programs) en_US
dc.title Compiler Optimizations for Multithreaded Multicore Network Processors en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Pande, Santosh
local.contributor.corporatename College of Computing
relation.isAdvisorOfPublication 6239fe5b-32c4-4067-9614-1ccca3374873
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
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