Title:
A Power Optimized Pipelined Analog-to-Digital Converter Design in Deep Sub-Micron CMOS Technology

dc.contributor.advisor Allen, Phillip E.
dc.contributor.author Cho, Chang-Hyuk en_US
dc.contributor.committeeMember Callen, W. Russell, Jr.
dc.contributor.committeeMember Kenney, James Stevenson
dc.contributor.committeeMember Leach, Marshall
dc.contributor.committeeMember Morley, Thomas
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2006-01-18T22:25:37Z
dc.date.available 2006-01-18T22:25:37Z
dc.date.issued 2005-11-28 en_US
dc.description.abstract High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology. The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed. A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mm CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 1564682 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/7578
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject CMOS analog circuits en_US
dc.subject Data converters
dc.title A Power Optimized Pipelined Analog-to-Digital Converter Design in Deep Sub-Micron CMOS Technology en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Allen, Phillip E.
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isAdvisorOfPublication 879a4c69-4f23-429a-bd1e-a3aad73ce2dd
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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