Title:
DENSE INTERCONNECTION AND ADVANCED COOLING TECHNOLOGIES FOR 2.5D AND 3D HETEROGENEOUS INTEGRATED CIRCUITS

dc.contributor.advisor Bakir, Muhannad S.
dc.contributor.advisor May, Gary S.
dc.contributor.author Kochupurackal Rajan, Sreejith
dc.contributor.committeeMember Frazier, Albert B.
dc.contributor.committeeMember Cressler, John D.
dc.contributor.committeeMember Krishna, Tushar
dc.contributor.committeeMember Joshi, Yogendra K.
dc.contributor.department Electrical and Computer Engineering
dc.date.accessioned 2022-05-18T19:38:26Z
dc.date.available 2022-05-18T19:38:26Z
dc.date.created 2022-05
dc.date.issued 2022-05-03
dc.date.submitted May 2022
dc.date.updated 2022-05-18T19:38:26Z
dc.description.abstract The objective of the proposed research is to design and demonstrate advanced interconnection and thermal management solutions for 2.5D and 3D heterogeneous ICs. Modern compute workloads require hardware capabilities which cannot be provided by the ever-slowing transistor scaling. This has driven the recent surge towards heterogeneous integration, where advanced 2.5D and 3D ICs complement System-on-Chip (SoC) innovations to provide high performance, low cost, and more customizable System-in-Packages (SiPs). In this work, we investigate enabling technologies that can help address the interconnection and thermal management issues in SiP scaling. First, we discuss a new interconnect platform that uses mechanical self-alignment in conjunction with metal electroless deposition as a method to facilitate low temperature, low pressure, and high interconnect density inter-die bonding in heterogeneous 2.5D and 3D ICs. This method is a highly scalable alternative to the conventional solder-based interconnects but comes without the stringent requirements such as high temperature tolerance, high pressure process, extreme surface planarity and cleanliness, and very accurate initial alignment requirements of Cu-Cu direct bonding. Secondly, the compute and cooling efficiency benefits of silicon-integrated monolithic microfluidic cooling were investigated on a high-power functional CPU running real-world benchmarks. Next, the technology was scaled to 2.5D architectures and was evaluated on an Intel FPGA with five discrete dice. Finite volume simulations and measurement data were used to quantify the benefits in terms of managing higher aggregate package power and minimizing the thermal coupling between closely spaced dice in 2.5D SiPs. Finally, the interconnection and thermal management co-design challenges were evaluated for a 3D stack with inter-layer microfluidic cooling. Fabrication optimizations for very high aspect ratio TSVs were developed and the thermal-electrical trade-offs for these vertical interconnects were analyzed using measurements and 3D-EM simulators.
dc.description.degree Ph.D.
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/66653
dc.language.iso en_US
dc.publisher Georgia Institute of Technology
dc.subject heterogeneous integration
dc.subject interconnects
dc.subject through silicon vias
dc.subject TSVs
dc.subject microfluidic cooling
dc.title DENSE INTERCONNECTION AND ADVANCED COOLING TECHNOLOGIES FOR 2.5D AND 3D HETEROGENEOUS INTEGRATED CIRCUITS
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Bakir, Muhannad S.
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isAdvisorOfPublication 752d9ed4-97ec-4a80-9920-4b4d3e762de1
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level Doctoral
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