Title:
Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures

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dc.contributor.advisor Lim, Sung Kyu
dc.contributor.author Healy, Michael Benjamin en_US
dc.contributor.committeeMember Lee, Hsien-Hsin
dc.contributor.committeeMember Loh, Gabriel
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2006-06-09T18:25:50Z
dc.date.available 2006-06-09T18:25:50Z
dc.date.issued 2006-04-12 en_US
dc.description.abstract The main objective of this thesis is to develop a physical design tool that is capable of being used by microarchitects to evaluate the impact of their design decisions on the physical design aspects of future microprocessor development. For deep submicron technology wire delay will scale increasingly badly compared to gate delay and so will become a major bottleneck to performance improvement. Three dimensional integrated circuits (3D ICs) offer a new method of dealing with non-linear wire latency by allowing shorter interconnects that act within their linear region. Thermal considerations in 3D ICs will be more important than traditional designs however, so this problem must also be addressed. This thesis presents a microarchitectural floorplanning tool that will help computer architects to attack the wire delay problem early in the design stages of higher performance microprocessors by including consideration of design for 3D ICs. Consideration of the new problems that occur due to the move to 3D and inherent difficulties with deep submicron design is included. Experiments demonstrate that this tool can generate microprocessor floorplans that include many objectives and continue to enhance performance into the next generation of high performance design. en_US
dc.description.degree M.S. en_US
dc.format.extent 390962 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/10562
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Temperature en_US
dc.subject Performance
dc.subject 3D integrated circuits
dc.subject Thermal distribution
dc.subject Floorplanning
dc.title Performance and Temperature Aware Floorplanning Optimization for 2D and 3D Microarchitectures en_US
dc.type Text
dc.type.genre Thesis
dspace.entity.type Publication
local.contributor.advisor Lim, Sung Kyu
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isAdvisorOfPublication 31bc3e86-9942-4b3f-aeae-783bb95052ff
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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