Title:
Enhancing microprocessor power efficiency through clock-data compensation
Enhancing microprocessor power efficiency through clock-data compensation
| dc.contributor.advisor | Raychowdhury, Arijit | |
| dc.contributor.author | Subramanian, Ashwin Srinath | |
| dc.contributor.committeeMember | Mukhopadhyay, Saibal | |
| dc.contributor.committeeMember | Wang, Hua | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2016-01-07T17:40:42Z | |
| dc.date.available | 2016-01-07T17:40:42Z | |
| dc.date.created | 2015-12 | |
| dc.date.issued | 2015-12-04 | |
| dc.date.submitted | December 2015 | |
| dc.date.updated | 2016-01-07T17:40:42Z | |
| dc.description.abstract | The Smartphone revolution and the Internet of Things (IoTs) have triggered rapid advances in complex system-on-chips (SoCs) that increasing provide more functionality within a tight power budget. Highly power efficient on die switched-capacitor voltage regulators suffer from large output voltage ripple preventing their widespread use in modern integrated circuits. With technology scaling and increasing architectural complexity, the number of transistors switching in a power domain is growing rapidly leading to major issues with respect to voltage noise. The large voltage and frequency guard-bands present in current microprocessor designs to combat voltage noise both degrade the performance and erode the energy efficiency of the design. In an effort to reduce guard-bands, adaptive clocking based systems combat the problem of voltage noise by adjusting the clock frequency during a voltage droop to avoid timing failure. This thesis presents an integrated power management and clocking scheme that utilizes clock-data compensation to achieve adaptive clocking. The design is capable of automatically con figuring the supply voltage given a target clock frequency for the load circuit. Furthermore, during a voltage droop the design adjusts clock frequency to meet critical path timing margins while simultaneously increasing the current delivered to the load to recover from the droop. The design was implemented in IBM's 130nm technology and simulation results show that the design is able to clock the load circuit from 30 MHz to 800 Mhz with current efficiencies as high as 97%. | |
| dc.description.degree | M.S. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/54471 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Power management | |
| dc.subject | Adaptive Clocking | |
| dc.subject | Clock-data compensation | |
| dc.subject | Power efficiency | |
| dc.title | Enhancing microprocessor power efficiency through clock-data compensation | |
| dc.type | Text | |
| dc.type.genre | Thesis | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Raychowdhury, Arijit | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | c44dbd39-c229-4ffb-9bc0-007eb0904114 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Masters |