Title:
Beyond-CMOS spintronic logic and ferroelectric memory
Beyond-CMOS spintronic logic and ferroelectric memory
| dc.contributor.advisor | Naeemi, Azad | |
| dc.contributor.author | Chang, Sou-Chi | |
| dc.contributor.committeeMember | Davis, Jeffrey | |
| dc.contributor.committeeMember | Mukhopadhyay, Saibal | |
| dc.contributor.committeeMember | Citrin, David | |
| dc.contributor.committeeMember | First, Phillip | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2017-01-11T14:03:09Z | |
| dc.date.available | 2017-01-11T14:03:09Z | |
| dc.date.created | 2016-12 | |
| dc.date.issued | 2016-10-04 | |
| dc.date.submitted | December 2016 | |
| dc.date.updated | 2017-01-11T14:03:09Z | |
| dc.description.abstract | The objective of this thesis is to explore spintronic logic and ferroelectric memory as potential solutions to beyond complementary metal-oxide-semiconductor (CMOS) technologies, since devices based on ferromagnetism and ferroelectricity hold great promise for the next-generation non-volatile digital computing and storage. In the first part of this thesis, novel device and interconnect structures using spintransfer torque (STT) on ferromagnetic metals and spin diffusive transport through non-magnetic materials are presented for low-power spintronic logic. Comprehensive physical models including spin injection, spin transport and stochastic magnetization dynamics are developed to justify the proposed concepts. On the other hand, recently ferroelectric tunnel junctions (FTJs) have been an active research topic in emerging memory technologies due to an extremely high on/off ratio originated from the giant tunneling electroresistance (TER) effect. Consequently, in the second part of this thesis, an original theoretical approach comprising quantum transport and thermodynamics is presented to describe measured I-V characteristics in various FTJs. Under the proposed formalism, the controversy of the opposite TER signs reported from different groups is explained by interface termination effects. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/56278 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Spintronic logic | |
| dc.subject | Ferroelectric memory | |
| dc.title | Beyond-CMOS spintronic logic and ferroelectric memory | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Naeemi, Azad | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | 6d1af007-99eb-4893-b4f9-e73991494499 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |