dc.contributor.advisor	Milor, Linda S.
dc.contributor.author	Kim, Woongrae
dc.contributor.committeeMember	Chatterjee, Abhijit
dc.contributor.committeeMember	Naeemi, Azad
dc.contributor.committeeMember	Schimmel, David
dc.contributor.committeeMember	Zhou, Haomin
dc.contributor.department	Electrical and Computer Engineering
dc.date.accessioned	2018-05-31T18:07:07Z
dc.date.available	2018-05-31T18:07:07Z
dc.date.created	2016-05
dc.date.issued	2016-03-29
dc.date.submitted	May 2016
dc.date.updated	2018-05-31T18:07:07Z
dc.description.abstract	The object of the proposed research is to develop comprehensive methodologies, including circuit design, new test methodologies, and statistical failure analysis, to implement reliable microprocessor and main memory systems. For a microprocessor, we have focused on the reliability issues in the embedded cache, since SRAMs are designed with the tightest design rules, and high performance processors are expected to consist of a large embedded memory. Also, to solve the scaling challenges for the main memory system, we have studied optimized design schemes for the 3D DRAM system, to achieve better performance, reliability, cost, and power.
dc.description.degree	Ph.D.
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1853/59737
dc.language.iso	en_US
dc.publisher	Georgia Institute of Technology
dc.subject	Reliability
dc.subject	SRAM
dc.subject	DRAM
dc.subject	Processor
dc.title	Design and test methodologies with statistical analysis for reliable memory and processor implementations
dc.type	Text
dc.type.genre	Dissertation
dspace.entity.type	Publication
local.contributor.advisor	Milor, Linda S.
local.contributor.corporatename	School of Electrical and Computer Engineering
local.contributor.corporatename	College of Engineering
relation.isAdvisorOfPublication	fbe5d5c9-48f4-4624-a928-ba45e51a4f54
relation.isOrgUnitOfPublication	5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication	7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level	Doctoral

Title: Design and test methodologies with statistical analysis for reliable memory and processor implementations

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Design and test methodologies with statistical analysis for reliable memory and processor implementations