Title:
Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability

dc.contributor.advisor Chatterjee, Abhijit
dc.contributor.author Dhillon, Yuvraj Singh en_US
dc.contributor.committeeMember Davis, Jeffrey A.
dc.contributor.committeeMember Habetler, Thomas
dc.contributor.committeeMember Singh, Adit
dc.contributor.committeeMember Wills, Scott
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2005-07-28T18:03:01Z
dc.date.available 2005-07-28T18:03:01Z
dc.date.issued 2005-04-20 en_US
dc.description.abstract Power consumption and soft-error tolerance have become major constraints in the design of DSM CMOS circuits. With continued technology scaling, the impact of these parameters is expected to gain in significance. Furthermore, the design complexity continues to increase rapidly due to the tremendous increase in number of components (gates/transistors) on an IC every technology generation. This research describes an efficient and general CAD framework for the optimization of critical circuit characteristics such as power consumption and soft-error tolerance under delay constraints with supply/threshold voltages and/or gate sizes as variables. A general technique called Delay-Assignment-Variation (DAV) based optimization was formulated for the delay-constrained optimization of directed acyclic graphs. Exact mathematical conditions on the supply and threshold voltages of circuit modules were developed that lead to minimum overall dynamic and static power consumption of the circuit under delay constraints. A DAV search based method was used to obtain the optimal supply and threshold voltages that minimized power consumption. To handle the complexity of design of reliable, low-power circuits at the gate level, a hierarchical application of DAV based optimization was explored. The effectiveness of the hierarchical approach in reducing circuit power and unreliability, while being highly efficient is demonstrated. The usage of the technique for improving upon already optimized designs is described. An accurate and efficient model for analyzing the soft-error tolerance of CMOS circuits is also developed. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 974160 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/6935
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Dual threshold voltages en_US
dc.subject Multiple supply voltages
dc.subject Low-power
dc.subject Sizing
dc.subject Circuit optimization
dc.subject Soft error
dc.title Hierarchical Optimization of Digital CMOS Circuits for Power, Performance and Reliability en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Chatterjee, Abhijit
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
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relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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