Top-Down MOSFET Fabrication of VLS-Grown Silicon Nanowires
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Kurup, Siddharth
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Abstract
Bottom-up nanoelectronic device synthesis presents an opportunity to achieve more scalable and customizable electronic circuitry. Vapor-liquid-solid (VLS) growth of semiconductor nanowires is enabling in this regard. While recent advances in bottom-up nanoscale patterning and area-selective deposition show a path to fully bottom-up field effect transistors (FETs), VLS growth can result in non-uniform doping, surface impurities, and other process-related imperfections that degrade performance relative to top-down fabricated devices. In this study, we combine current-voltage measurements with an analytical model to explore the process-structure-property relationships of Si FETs that combine VLS growth of the nanowire with top-down fabrication of the gate stack. We find that the low mobilities of devices using as-grown nanowires result from a combination of fixed charge scattering and surface roughness. A simple surface treatment of the nanowire (thermal oxidation followed by buffered oxide etch) before gate stack fabrication significantly improves effective mobility and reduces interface state density. Our study indicates the importance of post-VLS surface cleaning processes in the fabrication of high performance, fully bottom-up FETs.
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2025-04-11
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