Characterization of LDMOS Devices in the Deep Cryogenic Regime

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Kashyap, Avinash S.
Mantooth, H. A.
Mojarradi, M.
Mudholkar, M.
Vo, T.
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LDMOS devices are increasingly gaining attention as they aid in easier integration with existing CMOS technologies. They are especially used in applications requiring higher operating voltages such as power management circuits and high power amplifiers. The Jet Propulsion Laboratory (JPL) has developed LDMOS transistors using the existing IBM 5 AM technology to be used primarily in high voltage current mirrors in sensor interface circuits. These circuits are to be deployed in future lunar missions as part of a remote health monitoring system-on-a-chip that monitors the conditions surrounding key systems on a spacecraft. This chip processes a wide variety of possible sensor inputs through an analog front end (wheatstone bridge, variable gain amplifier, filtering, and data conversion). Most cryogenic studies of MOSFETs focus on normal lateral transistors and not on LDMOS devices. The authors have characterized and studied the operation of these devices in the deep cryo regime (~- 100 C to - 250 C). Normally, the characteristics of lateral MOSFETs improve with decreasing temperature. However, the asymmetrical nature of LDMOS devices, owing to the presence of a lightly doped drift region, causes the behavior to deviate from the expected characteristics at deep cryo temperatures. For example, the output current is expected to increase with decreasing temperature, but our observations indicate that the current initially increases and then starts decreasing after a certain transition temperature. This is attributed to the carrier freeze-out phenomenon occurring in the drift region due to lower ionization energies available to the carriers. The paper will report results on the breakdown, transfer and output characteristics of the JPL LDMOS devices as temperature decreases and attempt to explain the observation with physical reasoning.
Jet Propulsion Laboratory ; University of Arkansas
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