Title:
Managing signal, power, and thermal integrity for three-dimensional integrated circuits
Managing signal, power, and thermal integrity for three-dimensional integrated circuits
| dc.contributor.advisor | Swaminathan, Madhavan | |
| dc.contributor.author | Park, Sung Joo | |
| dc.contributor.committeeMember | Keezer, David | |
| dc.contributor.committeeMember | Lim, Sung-Kyu | |
| dc.contributor.committeeMember | Bakir, Muhannad | |
| dc.contributor.committeeMember | Joshi, Yogendra | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2017-08-17T18:57:25Z | |
| dc.date.available | 2017-08-17T18:57:25Z | |
| dc.date.created | 2016-08 | |
| dc.date.issued | 2016-07-20 | |
| dc.date.submitted | August 2016 | |
| dc.date.updated | 2017-08-17T18:57:25Z | |
| dc.description.abstract | A full thermal-electrical model of a 3-D system consisting of a PCB, an interposer, TSVs, and stacked dies was built and simulated. From the results of thermo-electrical simulations with clock distribution and power distribution network, temperature effects such as increased skew and noise in 3-D systems were quantified. To mitigate temperature-induced skew in a clock tree, three skew compensation methods using adaptive voltages, controllable delays, and variable strengths were proposed and their performance and design overhead were compared. As a verification procedure, two test vehicles using an FPGA and a custom IC have been designed and measured with implemented H-trees in test vehicles. Measurement results using the designed test vehicles with artificial temperature gradients are correlated with previous simulation results with the range of delay caused by temperature and compensation performance. Design optimization using the proposed thermal-electrical simulation approach requires large scale computing resources because of the number of parameters and multi-scale structure. Machine-learning approaches, a recent algorithm in artificial intelligence, are applied for the design optimization. Bayesian optimization using Gaussian process shows benefits for optimization of 3-D systems. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/58604 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | 3-D integration | |
| dc.subject | TSV | |
| dc.subject | Electrical-thermal | |
| dc.title | Managing signal, power, and thermal integrity for three-dimensional integrated circuits | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Swaminathan, Madhavan | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | 974f4642-b132-43e2-9ca6-c40e8af82f93 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |