Title:
Methodical Approximate Hardware Design and Reuse
Methodical Approximate Hardware Design and Reuse
Authors
Yazdanbakhsh, Amir
Thwaites, Bradley
Park, Jongse
Esmaeilzadeh, Hadi
Thwaites, Bradley
Park, Jongse
Esmaeilzadeh, Hadi
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Abstract
Design and reuse of approximate hardware components—digital circuits that may produce inaccurate results—can potentially lead to significant performance and energy improvements. Many emerging error-resilient applications can exploit such designs provided approximation is applied in a controlled manner. This paper provides the design abstractions and semantics for methodical, modular, and controlled approximate hardware design and reuse. With these abstractions, critical parts of the circuit still carry the strict semantics of traditional hardware design, while flexibility is provided. We discuss these abstractions in the context of synthesizable register transfer level (RTL) design with Verilog. Our framework governs the application of approximation during the synthesis process without involving the designers in the details of approximate synthesis and optimization. Through high-level annotations, our design paradigm provides high-level control over where and to what degree approximation is applied. We believe that our work forms a foundation for practical approximate hardware design and reuse.
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2014
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Technical Report