Title:
Reconfigurable Mixed-signal VLSI Implementation Of Distributed Arithmetic

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dc.contributor.patentcreator Ozalevli, Erhan
dc.contributor.patentcreator Hasler, Paul
dc.contributor.patentcreator Anderson, David Verl
dc.contributor.patentcreator Huang, Walter Geeshan
dc.date.accessioned 2017-05-12T14:28:30Z
dc.date.available 2017-05-12T14:28:30Z
dc.date.filed 8/17/2006
dc.date.issued 3/25/2008
dc.description.abstract Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.
dc.description.assignee Georgia Tech Research Corporation
dc.identifier.cpc H03M1/662
dc.identifier.patentapplicationnumber 11/465192
dc.identifier.patentnumber 7348909
dc.identifier.uri http://hdl.handle.net/1853/57732
dc.identifier.uspc 341/144
dc.title Reconfigurable Mixed-signal VLSI Implementation Of Distributed Arithmetic
dc.type Text
dc.type.genre Patent
dspace.entity.type Publication
local.contributor.corporatename Georgia Institute of Technology
local.relation.ispartofseries Georgia Tech Patents
relation.isOrgUnitOfPublication cc30e153-7a64-4ae2-9b1d-5436686785e3
relation.isSeriesOfPublication 0f49c79d-4efb-4bd9-b060-5c7f9191b9da
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