Opportunities for data-feedforward techniques for power prediction in digital systems
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Yin, Zheping
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Abstract
Efficient voltage regulation remains a significant challenge in modern digital systems. Conventional linear regulators respond slowly to load changes, so designers must add large voltage margins and decoupling capacitors. However, these fixes raise area and power costs.
We address this problem with a data‑feedforward technique that predicts the current draw in advance and trims the voltage margin. The system regulates an INT8 ML accelerator that skips multiply‑accumulate (MAC) operations with zero activations. A one‑bit metadata flag marks each activation, and an integrated clock‑gating (ICG) cell disables the corresponding MAC and flip-flops when the flag is zero.
A hardware current predictor complements the accelerator. The predictor contains a “mini accelerator” that is structurally identical to the main 4 × 4 PE array but built only from multiplexers. The “mini accelerator” runs one cycle ahead of the actual accelerator. The predictor counts metadata bits to estimate MAC and flip‑flop switching activity, then converts those counts into a current prediction with a least‑squares linear model.
We implemented the design in a TSMC65 LPLVT process and verified it from RTL to post‑APR. Post‑APR results show that zero‑skipping reduces switching power by 70% under sparse workloads. The predictor achieves an RMSE of 0.02% and consumes up to 10% of total system power. Tape‑out is scheduled for May 2025 to validate these results in silicon.
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2025-04-23
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Thesis (Masters Degree)