Ferroelectric Field Effect Transistors (FEFETs) With Gate Stack Engineering for Embedded and Storage Memory Applications
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Park, Chinsung
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Abstract
Advanced data-intensive computing models demand memory technologies that exceed conventional von Neumann architectures, requiring high-density and low-power capabilities. Among these emerging technologies, the ferroelectric field effect transistor (FEFET) stands out due to its advantages over other emerging technology devices. However, applying the FEFET to existing logic embedded or 3D NAND memory platforms presents several challenges. Firstly, the FEFET must satisfy logic compatibility for embedded applications, which requires a write voltage of less than 1.5 V, a memory window of greater than 0.5 V, and an endurance of over 1e10. Additionally, to be applied to a 3D NAND flash memory platform, the thickness of the FE stack must be less than 20 nm, and according to triple-level cell (TLC) standards, the memory window must exceed 6.5 V.
In the first part of this dissertation, gate stack engineering was utilized to achieve a logic-compatible FEFET by ensuring Vc <1.5 V. This research evaluated the correlation between various parameters of the gate stack (gate metal, ferroelectric layer, interfacial layer (IL), semiconductor, etc.) and Vc using MOS capacitors to identify parameters that enable a logic-compatible low write voltage. As a result, changes in the semiconductor (Ge substrate) and IL engineering (scavenging technique) proved to be the most effective for this purpose. It was also confirmed that the change of substrate from Si to Ge impacted IL reduction, demonstrating that IL has the greatest influence on Vc reduction. Finally, a FEFET with this gate stack structure was fabricated to verify the reduction of Vc. Additionally, evaluations of FEFETs on SOI substrates and the characteristics of Vc and memory window during ferroelectric layer deposition via thermal atomic layer deposition (ALD) and plasma-enhanced ALD were also conducted.
The second part of this dissertation focused on the application of a ferroelectric (FE) layer that meets two constraints: a thickness of FE less than 20 nm and a memory window (MW) greater than 6.5 V, within a 3D NAND flash platform. Theoretically, MW increases proportionally with the thickness of the FE layer, but a practical 20 nm FE layer cannot achieve MW > 3 V. Therefore, a structure with HZO thickness fixed at 10 nm and HZO/TiN layers stacked in series was considered, but the memory window could not meet the target (> 6.5 V). Consequently, a scheme was applied that involved inserting an Al2O3 layer into the FE layer. Initially, the validity of the evaluation stack was assessed using MOS capacitors, and then the actual MW was verified by fabricating FEFETs. The results confirmed an increase in MW greater than 7.5 V and a linear increase in MW with the thickness of Al2O3.
Thus, this dissertation work explores methods to engineer gate stacks to apply FE layers to two different application platforms. Achieving a low writing voltage for logic applications was addressed by adopting scavenging techniques and utilizing Ge semiconductor. The insertion of an Al2O3 layer was employed to attain a large MW for NAND applications, and these approaches were validated in FEFETs. This research, starting with MOS capacitors and culminating in the fabrication of FEFETs to validate the final gate stack, demonstrates how next-generation ferroelectric devices can be utilized for logic and 3D NAND flash applications. Future studies are needed to improve endurance using the gate stack engineering methods mentioned in this dissertation. Identifying avenues for improvement could lead to broader applications of FEFETs and expedite their commercialization.
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Date
2024-12-17
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Dissertation