Scheduling in Semiconductor Manufacturing
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Huertas Patino, Jorge Alberto
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Abstract
Semiconductors are a uniquely important enabling technology, fundamental to nearly all modern industrial activities. Scheduling in semiconductor manufacturing (SM) is a key driver of throughput and directly impacts the resilience of the global SM supply chain. However, the scheduling problems that arise in modern fabs are highly complex, and most facilities still rely on dispatching rules that are fast and easy to implement but struggle to enforce complex technological constraints—such as ensuring critical queue times (CQTs) between different operations—and remain myopic to high-quality solutions. Exact optimization models can represent these constraints in detail and aim for high-quality schedules but are often perceived as too slow or too rigid for industrial use. This thesis addresses this gap by developing advanced Constraint Programming (CP) models that exploit the fundamental structure of the scheduling problems that appear in wafer fabs. Some of the underlying structures are guided by different types of batching paradigms that arise at bottleneck areas in wafer fabs: parallel batching (p-batching) in the diffusion area and serial batching (s-batching) in the photolithography and ion implantation areas.
Chapter 3 dives into the p-batching problem in the diffusion area. The existing Aligned CP model (A) for p-batching with incompatible job families relies on specific alignment parameters in proprietary global constraints that are only available in one commercial solver to align the start and end times of jobs in the same batch. Chapter 3 presents four new solver-independent CP models that can be implemented in both commercial and open-source solvers, including the first automaton-based formulation in the literature for this problem. These solver-independent models lower barriers to adoption, both within semiconductor manufacturing and in other industries that face p-batching problems. These contributions are published in J. A. Huertas and P. Van Hentenryck, “Parallel batch scheduling with incompatible job families via constraint programming”, IEEE Transactions on Semiconductor Manufacturing, pp. 1–17, Aug. 2025. DOI: 10.1109/TSM.2025.3601510.
Building on this framework, Chapter 4 extends the A model by introducing family–machine dedications, multiple batch-bound functions on both the number of jobs and the aggregated number of parts, and single-step CQTs in the diffusion area, resulting in the A model with dedications (AD). All these extensions are motivated, guided, and validated by actual operational needs in real wafer fabrication facilities of an industry partner with next-generation foundries. The underlying family–machine dedications in the AD model induce a block-diagonal structure in the dedication matrix, which can be exploited to decompose the scheduling problem into several smaller independent subproblems that are solved efficiently in parallel. On real industrial instances from a leading manufacturer, the decomposed AD model solves schedules with nearly 500 jobs in a matter of seconds, provides optimality certificates for most subproblems, and produces schedules that are up to 13% better than the real performance of the fab, which is guided by dispatching rules that do not enforce key operational constraints that the AD model captures.
Chapter 5 switches to s-batching and presents the first three CP models for s-batching with minimum batch sizes, a key requirement in semiconductor manufacturing that has been rarely addressed. Furthermore, existing mixed-integer programming (MIP) methods in the literature can only tackle individual variants of s-batching and do not translate to other variants of the problem. In contrast, the proposed CP models, namely the Interval Assignment (IA), Global (G), and Hybrid (H) models, are versatile in nature and can tackle different s-batch variants with minimal changes considering: (i) item availability, preemptive batch processing, and flexible initiation, known as the IPF variant, which commonly appears in photolithography and ion implantation areas; and (ii) batch availability, and complete batch initiation, known as the BC variant, which typically arises in metal processing and related industries. Compared on over a thousand small to mid-size instances, the proposed CP models outperform existing MIP approaches and tabu search meta-heuristics, producing schedules up to 20% better than other methods while being up to six times faster. These contributions are published in J. A. Huertas and P. Van Hentenryck, “Constraint programming models for serial batch scheduling with minimum batch size”, Operations Research Perspectives, vol. 15, p. 100 352, Sep. 2025. DOI: 10.1016/j.orp.2025.100352.
Chapter 6 then brings key modeling insights from the p-batching models in Chapters 3 and 4 into the s-batching realm, resulting in an improved CP model specifically tailored for the IPF variant of s-batching with minimum batch sizes, typical of the ion implantation area. The new model is more compact, since it does not rely on the virtual set of possible batches required by the CP models in Chapter 5. Instead, it reasons directly on sequences of same-family jobs to enforce batch sizes. The resulting model outperforms the IA, G, and H models on the same instances. Furthermore, on nearly four thousand new instances with up to 500 jobs, the new model is capable of finding solutions up to 25% better than those produced by the models in Chapter~\ref{sec:s-batching_ORP}. These contributions are under review in J. A. Huertas and P. Van Hentenryck, “An aligned constraint programming model for serial batch scheduling with minimum batch size”, Under review in IEEE Transactions on Semiconductor Manufacturing, Nov. 2025. DOI: 10.48550/arXiv.2511.16045.
Finally, Chapter 7 integrates the proposed parallel and serial batching models into a flexible job shop scheduling framework that can represent multiple tool types in a wafer fab. This framework includes, for the first time in the literature, parallel batching tools, multiple batch bound functions, cluster tools with multiple chambers that process individual wafers and have setup requirements between wafers of different families, and multi-step CQTs. The resulting model is capable of individually schedule more than 8,000 wafers at the detailed chamber level. Tested on an industrial-size instance from a real wafer fab, the resulting model achieves a 13% improvement in overall throughput within just an hour of computation time. This model shows that it is possible to combine detailed scheduling representations with decomposition and problem structure to handle realistic fab configurations.
Overall, the thesis demonstrates that modern CP technology, when combined with problem-specific modeling that exploits underlying structure and leverages decomposition, can significantly narrow the gap between detailed optimization models for scheduling that enforce operational constraints and the dispatching rules used in current practice that cannot do so. The proposed models can serve as decision-support tools to benchmark and refine dispatching policies, or to generate high-quality reference schedules. In addition, the near-optimal solutions produced by these models open a path toward hybrid optimization and learning approaches, where modern AI methods are trained on the solutions of these CP models to design fast, learned schedulers that approximate near-optimal behavior in real time. In this sense, the contributions of the thesis provide both new scheduling tools for semiconductor manufacturing and a foundation for future work that combines exact optimization, machine learning, and discrete-event simulation for real-time decision support in wafer fabs.
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Date
2026-05
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Dissertation (PhD)