Title:
An Optimization Framework for Embedded Processors with Auto-Modify Addressing Modes

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dc.contributor.advisor Pande, Santosh
dc.contributor.author Lau, ChokSheak en_US
dc.contributor.committeeMember Christensen, Henrik I.
dc.contributor.committeeMember Dellaert, Frank
dc.contributor.committeeMember Essa, Irfan
dc.contributor.committeeMember Malik, Jitendra
dc.contributor.department Computing en_US
dc.date.accessioned 2005-03-01T19:34:05Z
dc.date.available 2005-03-01T19:34:05Z
dc.date.issued 2004-12-08 en_US
dc.description.abstract Modern embedded processors with dedicated address generation unit support memory accesses using indirect addressing mode with auto-increment and auto-decrement. The auto-increment/decrement mode, if properly utilized, can save address arithmetic instructions, reduce static and dynamic footprint of the program and speed up the execution as well. We propose an optimization framework for embedded processors based on the auto-increment and decrement addressing modes for address registers. Existing work on this class of optimizations focuses on using an access graph and finding the maximum weight path cover to find an optimized stack variables layout. We take this further by using coalescing, addressing mode selection and offset registers to find further opportunities for reducing the number of load-address instructions required. We also propose an algorithm for building the layout with considerations for memory accesses across basic blocks, because existing work mainly considers intra-basic-block information. We then use the available offset registers to try to further reduce the number of address arithmetic instructions after layout assignment. en_US
dc.description.degree M.S. en_US
dc.format.extent 579490 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/4856
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject 56300 en_US
dc.subject Motorola DSP56300
dc.subject Graph coloring
dc.subject Embedded systems
dc.subject Embedded processors
dc.subject Compiler optimization
dc.subject Offset assignment
dc.subject Address generation
dc.subject SOA
dc.subject GOA
dc.subject Coalesce
dc.subject Stack size
dc.subject GCC
dc.subject Address register
dc.subject Offset register
dc.subject Modify register
dc.subject Digital signal processing
dc.subject DSP
dc.subject Interference graph
dc.subject Access graph
dc.title An Optimization Framework for Embedded Processors with Auto-Modify Addressing Modes en_US
dc.type Text
dc.type.genre Thesis
dspace.entity.type Publication
local.contributor.advisor Pande, Santosh
local.contributor.corporatename College of Computing
local.relation.ispartofseries Master of Science in Computer Science
relation.isAdvisorOfPublication 6239fe5b-32c4-4067-9614-1ccca3374873
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
relation.isSeriesOfPublication 3ef9b3be-896e-4b1b-8aa6-e24d540b7d43
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