Title:
Chip-last Embedded Interconnect Structures
Chip-last Embedded Interconnect Structures
| dc.contributor.patentcreator | Liu, Fuhan | |
| dc.contributor.patentcreator | Kumbhat, Nitesh | |
| dc.contributor.patentcreator | Sundaram, Venkatesh | |
| dc.contributor.patentcreator | Tummala, Rao R. | |
| dc.date.accessioned | 2017-05-12T14:26:08Z | |
| dc.date.available | 2017-05-12T14:26:08Z | |
| dc.date.filed | 3/8/2012 | |
| dc.date.issued | 9/17/2013 | |
| dc.description.abstract | The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options. | |
| dc.description.assignee | Georgia Tech Research Corporation | |
| dc.identifier.cpc | H01L23/13 | |
| dc.identifier.cpc | H01L23/49827 | |
| dc.identifier.cpc | H01L23/49833 | |
| dc.identifier.patentapplicationnumber | 13/415503 | |
| dc.identifier.patentnumber | 8536695 | |
| dc.identifier.uri | http://hdl.handle.net/1853/56806 | |
| dc.identifier.uspc | 257/700 | |
| dc.title | Chip-last Embedded Interconnect Structures | |
| dc.type | Text | |
| dc.type.genre | Patent | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | Georgia Institute of Technology | |
| local.relation.ispartofseries | Georgia Tech Patents | |
| relation.isOrgUnitOfPublication | cc30e153-7a64-4ae2-9b1d-5436686785e3 | |
| relation.isSeriesOfPublication | 0f49c79d-4efb-4bd9-b060-5c7f9191b9da |
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