Title:
Timing Recovery Based on Per-Survivor Processing
Timing Recovery Based on Per-Survivor Processing
Author(s)
Kovintavewat, Piya
Advisor(s)
Barry, John R.
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Abstract
Timing recovery is the processing of synchronizing the sampler with the received analog signal. Sampling at the wrong times can have a devastating impact on performance. Conventional timing recovery techniques are based on a decision-directed phase-locked loop (PLL). They are adequate only when the operating signal-to-noise ratio (SNR) is sufficiently high, but recent advances in error-control coding have made it possible to communicate reliably at very low SNR, where conventional techniques fail. This thesis develops new techniques for timing recovery that are capable of working at low SNR.
We propose a new timing recovery scheme based on per-survivor processing (PSP), which jointly performs timing recovery and equalization, by embedding a separate PLL into each survivor of a Viterbi algorithm. The proposed scheme is shown to perform better than conventional scheme, especially when the SNR is low and the timing error is large. An important advantage of this technique is its amenability to real-time implementation.
We also propose a new iterative timing recovery scheme that exploits the presence of the error-control code; in doing so, it can perform even better than the PSP scheme described above, but at the expense of increased complexity and the requirement of batch processing. This scheme is realized by embedding the timing recovery process into a trellis-based soft-output equalizer using PSP. Then, this module iteratively exchanges soft information with the error-control decoder, as in conventional turbo equalization. The resulting system jointly performs the functions of timing recovery, equalization, and decoding. The proposed iterative timing recovery scheme is shown to perform better than previously reported iterative timing recovery schemes, especially when the timing error is severe.
Finally, performance analysis of iterative timing recovery schemes is difficult because of their high complexity. We propose to use the extrinsic information transfer (EXIT) chart as a tool to predict and compare their performances, considering that the bit-error rate computation takes a significant amount of simulation time. Experimental results indicate that the system performance predicted by the EXIT chart coincides with that obtained by simulating data transmission over a complete iterative receiver, especially when the coded block length is large.
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Date Issued
2004-10-13
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2177103 bytes
Resource Type
Text
Resource Subtype
Dissertation