Title:
Receiver Assembly And Method For Multi-gigabit Wireless Systems
Receiver Assembly And Method For Multi-gigabit Wireless Systems
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Abstract
The present invention describes a receiver assembly for receiving an analog signal and converting the analog signal to a digital signal. The receiver assembly is, preferably, capable of receiving a signal operating at approximately 60 GHz. The receiver assembly includes a filter, a down converter, a demodulator, a latch, a FIFO, and a logic circuit. A method of converting the 60 GHz analog signal to a digital signal is also described.
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Date Issued
9/22/2009
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Patent