Title:
System-level modeling and reliability analysis of microprocessor systems
System-level modeling and reliability analysis of microprocessor systems
| dc.contributor.advisor | Milor, Linda S. | |
| dc.contributor.author | Chen, Chang-Chih | |
| dc.contributor.committeeMember | Keezer, David | |
| dc.contributor.committeeMember | Naeemi, Azad | |
| dc.contributor.committeeMember | Chatterjee, Abhijit | |
| dc.contributor.committeeMember | Kim, Hyesoon | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2015-01-12T20:50:32Z | |
| dc.date.available | 2015-01-12T20:50:32Z | |
| dc.date.created | 2014-12 | |
| dc.date.issued | 2014-08-25 | |
| dc.date.submitted | December 2014 | |
| dc.date.updated | 2015-01-12T20:50:32Z | |
| dc.description.abstract | Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/53033 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Microprocessor | |
| dc.subject | Reliability | |
| dc.subject | Modeling | |
| dc.subject | Negative bias temperature instability | |
| dc.subject | Positive bias temperature instability | |
| dc.subject | Hot carrier injection | |
| dc.subject | Timing analysis | |
| dc.subject | Aging | |
| dc.subject | SRAM | |
| dc.subject | Cache | |
| dc.subject | Gate oxide breakdown | |
| dc.subject | Wearout | |
| dc.subject | Electromigration | |
| dc.subject | Stress-induced voiding | |
| dc.subject | Stress migration | |
| dc.subject | Time-dependent backend dielectric breakdown | |
| dc.title | System-level modeling and reliability analysis of microprocessor systems | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Milor, Linda S. | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | fbe5d5c9-48f4-4624-a928-ba45e51a4f54 | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |