Title:
Dynamic partitioned global address spaces for high-efficiency computing
Dynamic partitioned global address spaces for high-efficiency computing
dc.contributor.advisor | Yalamanchili, Sudhakar | |
dc.contributor.author | Young, Jeffrey | en_US |
dc.contributor.committeeMember | Riley, George | |
dc.contributor.committeeMember | Schimmel, David | |
dc.contributor.department | Electrical and Computer Engineering | en_US |
dc.date.accessioned | 2009-01-22T15:37:49Z | |
dc.date.available | 2009-01-22T15:37:49Z | |
dc.date.issued | 2008-11-19 | en_US |
dc.description.abstract | The current trend of ever larger clusters and data centers has coincided with a dramatic increase in the cost and power of these installations. While many efficiency improvements have focused on processor power and cooling costs, reducing the cost and power consumption of high-performance memory has mostly been overlooked. This thesis proposes a new address translation model called Dynamic Partitioned Global Address Space (DPGAS) that extends the ideas of NUMA and software-based approaches to create a high-performance hardware model that can be used to reduce the overall cost and power of memory in larger server installations. A memory model and hardware implementation of DPGAS is developed, and simulations of memory-intensive workloads are used to show potential cost and power reductions when DPGAS is integrated into a server environment. | en_US |
dc.description.degree | M.S. | en_US |
dc.identifier.uri | http://hdl.handle.net/1853/26467 | |
dc.publisher | Georgia Institute of Technology | en_US |
dc.subject | Partitioned global address space | en_US |
dc.subject | Memory | en_US |
dc.subject | Interconnects | en_US |
dc.subject | Efficiency | en_US |
dc.subject.lcsh | Computer storage devices | |
dc.subject.lcsh | Memory management (Computer science) | |
dc.subject.lcsh | Computer architecture | |
dc.subject.lcsh | Interconnects (Integrated circuit technology) | |
dc.title | Dynamic partitioned global address spaces for high-efficiency computing | en_US |
dc.type | Text | |
dc.type.genre | Thesis | |
dspace.entity.type | Publication | |
local.contributor.corporatename | School of Electrical and Computer Engineering | |
local.contributor.corporatename | College of Engineering | |
relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |
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