IPU/LTB: A Method for Reducing Effective Memory Latency
Author(s)
Appelbe, William
Das, Raja
Harmon, C. Reid, Jr.
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Abstract
This paper describes a new hardware approach to data and instruction
prefetching for superscalar processors. The key innovation is
instruction prefetching by predicting procedural control flow,
and decoupling data and instruction prefetching.
Simulation results show this method to recover 72% of unnecessarily
lost cache cycles and to yield a great improvement (20-27%) over
previous hardware prefetching techniques. The technique has a
relatively small cost in hardware, and is intended to come between
the processor and a level-1 cache.
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Date
1997
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317596 bytes
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Text
Resource Subtype
Technical Report