Title:
Future Branches -- Beyond Speculative Execution

dc.contributor.author Das, Raja
dc.contributor.author Harmon, C. Reid, Jr.
dc.contributor.author Appelbe, William en_US
dc.date.accessioned 2005-06-17T17:52:33Z
dc.date.available 2005-06-17T17:52:33Z
dc.date.issued 1997 en_US
dc.description.abstract Speculative execution of conditional branches has a high hardware cost, is limited by dynamic branch prediction accuracies, and does not scale well for increasingly superscalar architectures. Future branches are additional branch instructions that overcome the performance bottleneck of conventional branches. Future branch instructions includes a branch source address (the location of the impending conditional branch) as well as the branch target. The branch actually occurs when the program counter reaches the source address. If a future branch is executed before instruction fetching reaches the branch source, then there are no pipeline stalls or prediction necessary. Benchmark micro-architecture simulation studies show that at high superscalarities, losses to speculative execution consistently are higher than 10%, and these losses can be avoided by future branches. In addition, a hardware implementation of future branches for the PowerPC 604 has a very modest cost. en_US
dc.format.extent 193184 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/6659
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.relation.ispartofseries CC Technical Report; GIT-CC-97-33 en_US
dc.subject Future branches
dc.subject Speculative execution paradigm
dc.title Future Branches -- Beyond Speculative Execution en_US
dc.type Text
dc.type.genre Technical Report
dspace.entity.type Publication
local.contributor.corporatename College of Computing
local.relation.ispartofseries College of Computing Technical Report Series
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
relation.isSeriesOfPublication 35c9e8fc-dd67-4201-b1d5-016381ef65b8
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