Title:
Future Branches -- Beyond Speculative Execution
Future Branches -- Beyond Speculative Execution
Author(s)
Das, Raja
Harmon, C. Reid, Jr.
Appelbe, William
Harmon, C. Reid, Jr.
Appelbe, William
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Abstract
Speculative execution of conditional branches
has a high hardware cost, is limited by dynamic branch
prediction accuracies, and does not scale well for increasingly
superscalar architectures.
Future branches are additional branch instructions that
overcome the performance bottleneck of conventional branches.
Future branch instructions includes a branch source address (the
location of the impending conditional branch) as well as the branch
target. The branch actually occurs when the program counter reaches
the source address. If a future branch is executed
before instruction fetching reaches the branch source,
then there are no pipeline stalls or prediction necessary.
Benchmark micro-architecture simulation studies show that at high
superscalarities, losses to speculative execution consistently are
higher than 10%, and these losses can be avoided by future branches.
In addition, a hardware implementation of future branches for the PowerPC
604 has a very modest cost.
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Date Issued
1997
Extent
193184 bytes
Resource Type
Text
Resource Subtype
Technical Report