Title:
Near-memory primitive support and infratructure for sparse algorithm

dc.contributor.advisor Yalamanchili, Sudhakar
dc.contributor.advisor Young, Jeffrey
dc.contributor.author Garg, Kartikay
dc.contributor.committeeMember Krishna, Tushar
dc.contributor.committeeMember Vuduc, Richard
dc.contributor.department Electrical and Computer Engineering
dc.date.accessioned 2017-06-07T17:49:45Z
dc.date.available 2017-06-07T17:49:45Z
dc.date.created 2017-05
dc.date.issued 2017-04-28
dc.date.submitted May 2017
dc.date.updated 2017-06-07T17:49:45Z
dc.description.abstract This thesis introduces an approach to solving the problem of memory latency performance penalties with traditional accelerators. By introducing simple near-data-processing (NDP) accelerators for primitives such as SpMV (Sparse Matrix Multiplication of Vectors) and DGEMM (Double Precision Dense Matrix Multiplication) kernels, applications can achieve a considerable performance boost. We evaluate our work for SuperLU application for the HPC community. Thesis Statement: Reevaluating core primitives such as DGEMM, SCATTER, and GATHER for 3D-stacked PIM architectures that incorporate re-configurable fabrics can deliver multi-fold performance improvements for SUPERLU and other sparse algorithms.
dc.description.degree M.S.
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/58343
dc.language.iso en_US
dc.publisher Georgia Institute of Technology
dc.subject Processing in memory (PIM)
dc.subject Near data processing (NDP)
dc.subject 3D-stacked memory
dc.subject HMC
dc.subject FPGA
dc.subject SuperLU
dc.title Near-memory primitive support and infratructure for sparse algorithm
dc.type Text
dc.type.genre Thesis
dspace.entity.type Publication
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level Masters
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