Title:
Quarter-square Analog Four-Quadrant Multiplier Using Mos Integrated Circuit Technology
Quarter-square Analog Four-Quadrant Multiplier Using Mos Integrated Circuit Technology
| dc.contributor.patentcreator | Pena-finol, Jesus S. | |
| dc.contributor.patentcreator | Connelly, Joseph A. | |
| dc.date.accessioned | 2017-05-12T14:28:06Z | |
| dc.date.available | 2017-05-12T14:28:06Z | |
| dc.date.filed | 6/2/1983 | |
| dc.date.issued | 10/8/1985 | |
| dc.description.abstract | A four-quadrant NMOS transconductance multiplier including plural NMOS transistors formed in a substrate to produce a pair of summer stages and a pair of squaring stages which process a pair of input signals V1, V2 to produce an output signal Vo according to the quarter-square algebraic identity, Vo =1/4[(V1 +V2)2 -(V1 -V2)2 ]=V1 V2.In a preferred embodiment, the substrate doping NA =6.7X10^15 cm-3 and the channel width and channel length of each of the NMOS transistors forming the summer and squaring stages is greater than 10 ?m. | |
| dc.description.assignee | Georgia Tech Research Institute | |
| dc.identifier.cpc | G06G7/164 | |
| dc.identifier.patentapplicationnumber | 06/500540 | |
| dc.identifier.patentnumber | 4546275 | |
| dc.identifier.uri | http://hdl.handle.net/1853/57587 | |
| dc.identifier.uspc | 327/357 | |
| dc.title | Quarter-square Analog Four-Quadrant Multiplier Using Mos Integrated Circuit Technology | |
| dc.type | Text | |
| dc.type.genre | Patent | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | Georgia Institute of Technology | |
| local.relation.ispartofseries | Georgia Tech Patents | |
| relation.isOrgUnitOfPublication | cc30e153-7a64-4ae2-9b1d-5436686785e3 | |
| relation.isSeriesOfPublication | 0f49c79d-4efb-4bd9-b060-5c7f9191b9da |
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