Design-Technology Co-Optimization of Ferroelectric Devices for Capacitive In-Memory Computing and On-Chip Buffers

Ferroelectric memories have been widely investigated for both analog Compute-In-Memory (CIM) and buffer memory applications. In conventional analog CIM, weights are represented by the conductance of non-volatile resistive memories. However, these resistive memory arrays suffer from high static power, serious IR drop, and sneak-path issues. To overcome these challenges, ferroelectric “capacitive” crossbar arrays are proposed in this thesis since the capacitive approach (1) only consumes dynamic power, (2) has no DC sneak paths, (3) avoids IR drop along wires, and (4) has a high 3D stacking potential. In this thesis, ferroelectric capacitive crossbar arrays are investigated from device physics, device/array measurement, circuit simulation, to system-level benchmarking, where a cross-layer framework is built to connect the device and circuit parameters to system-level metrics. On the other hand, ferroelectric non-volatile memories as embedded storage units are also investigated. More specifically, an endurance-aware compiler is built to estimate the impact of the endurance issues of Ferroelectric Random-Access Memory (FeRAM) on system lifetime; 2T1F FeRAM is proposed for its ultra-compact cell area and low-power characteristics compared to the conventional 1T1F FeRAM; The temperature dependency of FeRAM endurance and sense margins will also be analyzed. Besides FeRAM, two other ferroelectric on-chip memories will be introduced. First, a ferroelectric non-volatile SRAM will be investigated due to its zero-leakage and instant-on advantages for edge devices with low active rates. Finally, a ferroelectric tunnel junction with high on/off ratios and multiple memory states per cell will be demonstrated.

Date

2024-04-27

Resource Type

Text

Resource Subtype

Dissertation

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