Algorithm-Hardware Co-design for Deep Learning and Probabilistic Computing with Compute-in-Memory Accelerators
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Lu, Anni
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Abstract
Compute-in-memory (CIM) is an attractive solution to accelerate the multiply-accumulate (MAC) operations of deep learning and beyond due to its high processing parallelism and energy efficiency. In this thesis, algorithm-hardware co-optimizations of CIM are explored across diverse models and applications. First, the integrated benchmark framework “NeuroSim” for CIM accelerators is validated with actual silicon data and calibrated with adjustment factors. Based on this simulator, the CIM systems for deep neural network (DNN) with limited on-chip resources are explored, addressing the challenge of accommodating large-scale models on area-constrained CIM chips, and the reconfiguration of deploying different models on prefabricated CIM chip with fixed hardware resources.
The CIM scheme is further extended to probabilistic computing, where the memory and circuit intrinsic stochasticity are no longer harmful to model accuracy but provides energy-efficient random number generation. A novel CIM accelerator for Bayesian neural network is proposed to generate Gaussian distributed weights using the probabilistic switching of spin-orbit torque magnetic random-access memory (SOT-MRAM) in weak programming. The inherent memory noise is also utilized for scalable in-memory Ising annealers to solve NP-hard combinatorial optimization problems. An analog CIM annealer using temporal variation of charge-trap transistor and a digital CIM annealer using process variation of static random-access memory (SRAM) are proposed. Design space explorations and system-level performance evaluations are also performed by modifying the validated NeuroSim simulator.
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2024-04-27
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Dissertation