A low-power subranging oversampling two-stage SAR ADC design
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Belgorod, Gregory Arlington
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Abstract
This thesis presents a two-stage successive approximation register (SAR) digital-to-analog converter (DAC) with a first-stage continuous-time (CT) SAR ADC. This is done to reduce the sampling noise that would otherwise be generated with a standard sample-and-hold (S/H) front-end architecture. This circuit concept also is embedded with noise shaping, error feedback, gain error correction, subranging, and embedded buffering capabilities. These features are included with the objective of helping to combat noise and to improve output accuracy. To verify the viability of the circuit and the functionality of the embedded features, Cadence simulations utilizing 65 nm CMOS technology were conducted, using a sampling frequency of 1 MHz and an oversampling ratio (OSR) of 8. The design achieved an SNDR of 90.04 dB, an ENOB of 14.66 bits, a Schreier Figure of Merit of 180.36 dB, and only consumed 57.52 uW of power.
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2023-04-25
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Thesis