Engineering a self-aligned metal-oxide-semiconductor gate stack for nano-modular device fabrication

By shifting the existing semiconductor fabrication paradigm and embracing scalable, bottom-up manufacturing techniques, fully formed high-performance transistors can be produced and interconnected for low-cost fabrication of customizable circuitry. For example, high-performance modular nanowire transistors can be synthesized using bulk processing methods. The pre-fabricated devices can be deposited on a substrate, and metal interconnects can be adaptively printed to form circuits. This work focuses on developing a self-aligned gate stack that would enable the production of bottom-up nanowire electronic devices and on understanding how material deposition and post-processing impacts performance of the devices. To investigate the gate stack materials, this work adapts a selective, bottom-up polymer patterning process for planar Si substrates to fabricate and characterize self-aligned metal-oxide-semiconductor (MOS) capacitor devices. Selectivity of deposition is investigated for a variety of oxides and metals via area-selective atomic layer deposition, and ultimately hafnium oxide (HfO2) and platinum are determined to be the optimal materials system. The quality of the oxide-semiconductor interface is particularly important for MOS device performance, so the HfO2-Si interface is investigated in detail by examining different SiO2 interlayer formation techniques. Physical characterization is used to understand the relationship between the interlayer formation and electrical performance. In summary, this work develops a self-aligned gate stack fabrication process and investigates the impact of processing on the electrical performance of the materials. And this self-aligned gate stack deposition process provides a pathway towards fabricating modular nanowire transistors.

Date

2023-04-25

Resource Type

Text

Resource Subtype

Dissertation

Full item page