3nm Nanosheet FET vs. FinFET Comparison and Optimization with device/circuit co-design framework
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Shaji, Sandra Maria
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Abstract
This work presents a device/circuit co-design framework that encompasses device, interconnect, cell, and full-chip. Using this framework, we quantitatively compare vertically stacked Nanosheet FET (NSFET) vs. FinFET technologies at 3nm using full-chip power, performance, area (PPA) metrics. Additionally, we enhance the flow to identify and optimize key device parameters that affect full-chip PPA. Our experiments show that our 3nm NSFET technology offers 15% reduced device capacitance translating to 22%, and 6% power savings over FinFET at the cell and full-chip level, respectively. Our NSFET device parameter optimization further improves performance and power by upto 44\% and 28% respectively.
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2023-05-02
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