Translating GPU Binaries to Tiered SIMD Architectures with Ocelot
Author(s)
Diamos, Gregory
Kerr, Andrew
Kesavan, Mukil
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Abstract
Parallel Thread Execution ISA (PTX) is a virtual
instruction set used by NVIDIA GPUs that explicitly expresses
hierarchical MIMD and SIMD style parallelism in an application.
In such a programming model, the programmer and compiler
are left with the not trivial, but not impossible, task of composing
applications from parallel algorithms and data structures. Once
this has been accomplished, even simple architectures with low
hardware complexity can easily exploit the parallelism in an
application.
With these applications in mind, this paper presents Ocelot,
a binary translation framework designed to allow architectures
other than NVIDIA GPUs to leverage the parallelism in PTX
programs. Specifically, we show how (i) the PTX thread hierarchy
can be mapped to many-core architectures, (ii) translation
techniques can be used to hide memory latency, and (iii) GPU
data structures can be efficiently emulated or mapped to native
equivalents. We describe the low level implementation of our
translator, ending with a case study detailing the complete
translation process from PTX to SPU assembly used by the IBM
Cell Processor.
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Date
2009
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Text
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Technical Report