Performance estimation of large area nanowires

Kamdar, Keval Prakash

Title:

Performance estimation of large area nanowires

dc.contributor.advisor	Raychowdhury, Arijit
dc.contributor.author	Kamdar, Keval Prakash
dc.contributor.committeeMember	Lim, Sung-Kyu
dc.contributor.committeeMember	Khan, Asif
dc.contributor.department	Electrical and Computer Engineering
dc.date.accessioned	2019-05-29T14:04:49Z
dc.date.available	2019-05-29T14:04:49Z
dc.date.created	2019-05
dc.date.issued	2019-04-30
dc.date.submitted	May 2019
dc.date.updated	2019-05-29T14:04:49Z
dc.description.abstract	The focus of the thesis is to extensively model high-performance nanowires, develop Verilog A models of the devices and then simulate them using SPICE to estimate their power-performance trade-offs. Once the device models are created, they will be used in circuits which will have realistic interconnects with necessary parasitic resistance and impedance (inductance and capacitance) and simulated for prototypical digital and mixed signal designs. The device and the circuit simulation infrastructure will be developed in parallel. Synopsys Taurus and Medici will be used for 3D device modelling, Verilog A for circuit-compatible models, and Spice for circuit and system evaluation.
dc.description.degree	M.S.
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1853/61309
dc.language.iso	en_US
dc.publisher	Georgia Institute of Technology
dc.subject	Nanowires
dc.subject	vlsi
dc.title	Performance estimation of large area nanowires
dc.type	Text
dc.type.genre	Thesis
dspace.entity.type	Publication
local.contributor.advisor	Raychowdhury, Arijit
local.contributor.corporatename	School of Electrical and Computer Engineering
local.contributor.corporatename	College of Engineering
relation.isAdvisorOfPublication	c44dbd39-c229-4ffb-9bc0-007eb0904114
relation.isOrgUnitOfPublication	5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication	7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level	Masters