A 1.5V Multirate Multibit Sigma Delta Modulator for GSM/WCDMA in a 90nm Digital CMOS Process

dc.contributor.advisor Allen, Phillip E.
dc.contributor.author Altun, Oguz en_US
dc.contributor.committeeMember Ayazi, Farrokh
dc.contributor.committeeMember Laskar, Joy
dc.contributor.committeeMember Leach, Marshall W.
dc.contributor.committeeMember Morley, Tom
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2005-09-16T14:58:06Z
dc.date.available 2005-09-16T14:58:06Z
dc.date.issued 2005-04-18 en_US
dc.description.abstract A dual-mode second-order Multirate Multibit Sigma Delta (MM-SD) modulator is implemented in a 90nm digital CMOS process for application in the baseband path of RF receivers. Low power consumption is achieved through a new integrator structure and a dedicated timing scheme along with aggressive capacitor scaling in the second stage of the modulator loop. Fabricated prototype achieves 68.6dB peak Signal-to-Noise and Distortion ratio (SNDR) in the 200 kHz GSM band and requires 1.1mA of total current from a 1.5V supply. This dual-mode design also achieves 42.8dB SNDR in the 1.94 MHz WCDMA band with only 1.9mA of total current consumption. en_US
dc.description.degree Ph.D. en_US
dc.format.extent 1067977 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/7104
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.subject Low-power en_US
dc.subject Mixed-signal
dc.subject Low voltage
dc.subject Sigma delta modulators
dc.title A 1.5V Multirate Multibit Sigma Delta Modulator for GSM/WCDMA in a 90nm Digital CMOS Process en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Allen, Phillip E.
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
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relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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