Adaptive Backscatter Communication Approach for Next-Generation Biotelemetry Applications
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Kasina, Bindu Madhavi
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Abstract
This thesis presents the design and implementation of a Proof of Concept (POC) system that adaptively distributes logic gate resources of an Application Specific Integrated Circuit (ASIC) between RFID backscattering and sensor data processing. This work is an extension for the application of digital logic in RFID backscattering systems. The system utilizes the electronic switching capabilities of CMOS transistors within logic gates to create impedance variations between high and low states, effectively altering the Radar Cross Section (RCS) and thereby modulating the backscattered field.
The enhancement detailed in this thesis is the adaptive distribution of logic gate resources based on received signal power at the reader. A POC system is described in our work, where the reader classifies the received power as low or sufficient. If the received power is low, this information can be encoded into the carrier wave. This carrier wave is incident on the tag, where the tag performs two important tasks: 1) The control circuit decodes the control input from the carrier wave (This part is not in the scope of this Thesis.). 2) The FPGA receives this input and adaptively adjusts the amount of logic gate resources. In addition, the signal incident on the tag is modulated via backscattering from the FPGA’s chip. Hence, the FPGA’s chip is also responsible for the backscattering. The primary focus of this work is to enhance the received backscattered signal power by dynamically modifying the amount of logic gate resources on the FPGA based on a given control input. We detail how information received at the FPGA is utilized to make these adaptive adjustments. We also present the algorithm used to program the FPGA to enable this functionality. The practical implications of our work are demonstrated through successful measurements, which indicate that higher logic gate utilization correlates directly with increased received power. Our results show up to a 7dB improvement in received power when logic gate utilization of the FPGA is increased from 30% to 100%. We have also provided results showing that the system adaptively changes the logic gate utilization without the need for reprogramming the FPGA, using internal and external control logic to adjust the logic gate resources dynamically. In summary, this thesis aims to develop a fully self-sufficient RFID system that facilitates real-time adjustments to backscattering logic gate resources in the ASIC/FPGA based on the strength of the signal received at the reader. The findings from this study provide a solid foundation for the development of an adaptive RFID ASIC system for biotelemetry applications
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Date
2024-04-29
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