Title:
Stress Relieving Second Level Interconnect Structures And Methods Of Making The Same

dc.contributor.patentcreator Raj, Pulugurtha Markondeya
dc.contributor.patentcreator Kumbhat, Nitesh
dc.contributor.patentcreator Sundaram, Venkatesh V.
dc.contributor.patentcreator Tummala, Rao R.
dc.contributor.patentcreator Qin, Xian
dc.date.accessioned 2017-05-12T14:26:34Z
dc.date.available 2017-05-12T14:26:34Z
dc.date.filed 9/20/2011
dc.date.issued 3/3/2015
dc.description.abstract Provided is a stress-relieving, second-level interconnect structure that is low-cost and accommodates thermal coefficient of expansion (TCE) mismatch between low-TCE packages and printed circuit boards (PCBs). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, thereby enhancing compliance between the two electronic components.
dc.description.assignee Georgia Tech Research Corporation
dc.identifier.cpc H05K3/3436
dc.identifier.cpc H05K3/4007
dc.identifier.cpc H01L24/11
dc.identifier.patentapplicationnumber 13/825815
dc.identifier.patentnumber 8970036
dc.identifier.uri http://hdl.handle.net/1853/56965
dc.identifier.uspc 257/737
dc.title Stress Relieving Second Level Interconnect Structures And Methods Of Making The Same
dc.type Text
dc.type.genre Patent
dspace.entity.type Publication
local.contributor.corporatename Georgia Institute of Technology
local.relation.ispartofseries Georgia Tech Patents
relation.isOrgUnitOfPublication cc30e153-7a64-4ae2-9b1d-5436686785e3
relation.isSeriesOfPublication 0f49c79d-4efb-4bd9-b060-5c7f9191b9da
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