Title:
Optimizing high locality memory references in cache coherent shared memory multi-core processors
Optimizing high locality memory references in cache coherent shared memory multi-core processors
| dc.contributor.advisor | Yalamanchili, Sudhakar | |
| dc.contributor.author | Kang, Suk Chan | |
| dc.contributor.committeeMember | Wills, Linda | |
| dc.contributor.committeeMember | Gavrilovska, Ada | |
| dc.contributor.committeeMember | Krishna, Tushar | |
| dc.contributor.committeeMember | Pande, Santosh | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2020-05-20T16:47:54Z | |
| dc.date.available | 2020-05-20T16:47:54Z | |
| dc.date.created | 2019-05 | |
| dc.date.issued | 2019-01-11 | |
| dc.date.submitted | May 2019 | |
| dc.date.updated | 2020-05-20T16:47:54Z | |
| dc.description.abstract | Optimizing memory references has been a primary research area of computer systems ever since the advent of the stored program computers. The objective of this thesis research is to identify and optimize two classes of high locality data memory reference streams in cache coherent shared memory multi-processors. More specifically, this thesis classifies such memory objects into spatial and temporal false shared memory objects. The underlying hypothesis is that the policy of treating all the memory objects as being permanently shared significantly hinders the optimization of high-locality memory objects in modern cache coherent shared memory multi-processor systems: the policy forces the systems to unconditionally prepare to incur shared-memory-related overheads for every memory reference. To verify the hypothesis, this thesis explores two different schemes to minimize the shared memory abstraction overheads associated with memory reference streams of spatial and temporal false shared memory objects, respectively. The schemes implement the exception rules which enable isolating false memory objects from the shared memory domain, in a spatial and temporal manner. However, the exception rules definitely require special consideration in cache coherent shared memory multi-processors, regarding the data consistency, cache coherence, and memory consistency model. Thus, this thesis not only implements the schemes based on such consideration, but also breaks the chain of the widespread faulty assumption of prior academic work. This high-level approach ultimately aims at upgrading scalability of large scale systems, such as multi-socket cache coherent shared memory multi-processors, throughout improving performance and reducing energy/power consumption. This thesis demonstrates the efficacy and efficiency of the schemes in terms of performance improvement and energy/power reduction. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/62641 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Shared memory system | |
| dc.subject | Cache coherence | |
| dc.subject | Memory consistency | |
| dc.subject | Synchronization | |
| dc.title | Optimizing high locality memory references in cache coherent shared memory multi-core processors | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |