Title:
Embedded Actives And Discrete Passives In A Cavity Within Build-up Layers
Embedded Actives And Discrete Passives In A Cavity Within Build-up Layers
| dc.contributor.patentcreator | Lee, Baik-woo | |
| dc.contributor.patentcreator | Yoon, Chong | |
| dc.contributor.patentcreator | Sundaram, Verkatesh | |
| dc.contributor.patentcreator | Tummala, Rao | |
| dc.date.accessioned | 2017-05-12T14:25:54Z | |
| dc.date.available | 2017-05-12T14:25:54Z | |
| dc.date.filed | 7/27/2006 | |
| dc.date.issued | 12/18/2012 | |
| dc.description.abstract | Disclosed are any electronic system or module which includes embedded actives and discrete passives, and methods for use in fabricating packages containing embedded active devices and/or discrete passive devices. Exemplary apparatus comprises a plurality of build-up layers defining circuit interconnections and that comprise one or more thin film type of embedded passive devices, at least a cavity formed in the build-up layers, and at least an active device and/or at least a discrete passive device disposed in the cavity and electrically connected to the circuit interconnections of the build-up layers. A stiffener may be coupled to an exposed (back) surface of the active device and to an adjacent surface of the build-up layers. The build-up layers may be mounted to a core, and the core may be attached to a printed circuit board. Alternatively, a bottom surface of the build-up layers may be mounted to a printed circuit board without core. The packages have a chip reworkability, an easier thermal management, a very thin profile and enhanced electrical performance comparable to packages produced using chip-first or chip-middle approaches. | |
| dc.description.assignee | Georgia Tech Research Corporation | |
| dc.identifier.cpc | H01L23/49822 | |
| dc.identifier.cpc | H01L23/5389 | |
| dc.identifier.cpc | H05K1/183 | |
| dc.identifier.patentapplicationnumber | 11/494259 | |
| dc.identifier.patentnumber | 8335084 | |
| dc.identifier.uri | http://hdl.handle.net/1853/56722 | |
| dc.identifier.uspc | 361/720 | |
| dc.title | Embedded Actives And Discrete Passives In A Cavity Within Build-up Layers | |
| dc.type | Text | |
| dc.type.genre | Patent | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | Georgia Institute of Technology | |
| local.relation.ispartofseries | Georgia Tech Patents | |
| relation.isOrgUnitOfPublication | cc30e153-7a64-4ae2-9b1d-5436686785e3 | |
| relation.isSeriesOfPublication | 0f49c79d-4efb-4bd9-b060-5c7f9191b9da |
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