Title:
Investigating Opportunities and Challenges in Modeling and Designing Scale-Out DNN Accelerators
Investigating Opportunities and Challenges in Modeling and Designing Scale-Out DNN Accelerators
Authors
Nadella, Vineet
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Advisors
Krishna, Tushar
Mukhopadhyay, Saibal
Daglis, Alexandros
Mukhopadhyay, Saibal
Daglis, Alexandros
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Abstract
The rapid growth of deep learning used in practical applications such as speech recognition,
computer vision, natural language processing, robotics, any many other fields has opened
the gate to new technology possibilities. Unfortunately, traditional hardware systems
are being stretched to the maximum to accommodate the intense workloads presented by
state-of-the-art deep learning processes in a time when transistor technology is not scaling.
To serve the demand for better computational power and more specialized computations,
specialized hardware needs to be developed that provides better latency and bandwidth
specifications for various demanding applications.
The trend in the semi-conductor industry is to move towards heterogenous System-On
Chip (SoC) thereby choosing application specific performance vs. generality seen in most
CPU architectures today. In most situations, hardware engineers are left to construct
systems that serve the needs of various applications, often needing to predict the use-cases
of the system. As with any field, the ability to predict and act on the future innovation
trends of the industry is the difference between success and failure.
A novel simulator for the design of convolutional neural network accelerators is
presented and described in detail named SCALE-Sim (Systolic CNN Accelerator
Simulator). The simulator is available as an open-sourced repository and has 2 primary
use-cases in which computer architects can extract significant results. The first use-case is
for system designers who would like to integrate an existing DNN accelerator architecture
into a larger SoC and would be interested in system-level characterization results. The
second use-case is for an accelerator architect who would like to use the tool to explore the
accelerator design space by sweeping through design parameters.
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Date Issued
2020-04-28
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