Title:
Round-robin Arbiter Design and Generation
Round-robin Arbiter Design and Generation
| dc.contributor.author | Shin, Eung Seo | en_US |
| dc.contributor.author | Mooney, Vincent John, III | |
| dc.contributor.author | Riley, George F. | |
| dc.date.accessioned | 2005-06-17T17:41:03Z | |
| dc.date.available | 2005-06-17T17:41:03Z | |
| dc.date.issued | 2002 | en_US |
| dc.description.abstract | In this paper, we introduce a Roundrobin Arbiter Generator (RAG) tool. The RAG tool can generate a design for a Bus Arbiter (BA). The BA is able to handle the exact number of bus masters for both on-chip and off-chip buses specified by the user of RAG. RAG can also generate a distributed and parallel hierarchical Switch Arbiter (SA). The first contribution of this paper is the automated generation of a round-robin token passing BA to reduce time spent on arbiter design. The generated arbiter is fair, fast, and has a low and predictable worst-case wait time. The second contribution of this paper is the design and integration of a distributed fast arbiter, e.g., for a terabit switch, based on 4x4 and 2x2 switch arbiters (SAs). Using a .25 TSMC standard cell library from LEDA Systems [11, 15], we show the arbitration time of a 256x256 SA for a terabit switch and demonstrate that the SA generated by RAG meets the time constraint to achieve approximately six terabits of throughput in a typical network switch design. Furthermore, our generated SA performs better than the Ping-Pong Arbiter and Programmable Priority Encoder by a factor of 1.9X and 2.4X, respectively. | en_US |
| dc.format.extent | 389536 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/6545 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.relation.ispartofseries | CC Technical Report; GIT-CC-02-38 | en_US |
| dc.subject | Roundrobin Arbiter Generator tool | |
| dc.subject | Switch arbiter | |
| dc.subject | Bus architecture | |
| dc.title | Round-robin Arbiter Design and Generation | en_US |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.author | Mooney, Vincent John, III | |
| local.contributor.corporatename | College of Computing | |
| local.relation.ispartofseries | College of Computing Technical Report Series | |
| relation.isAuthorOfPublication | 1068070d-f7e9-4b9c-9be6-72023d13e2a1 | |
| relation.isOrgUnitOfPublication | c8892b3c-8db6-4b7b-a33a-1b67f7db2021 | |
| relation.isSeriesOfPublication | 35c9e8fc-dd67-4201-b1d5-016381ef65b8 |
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