Exploiting on-chip memory concurrency in 3d manycore architectures

Hassan, Syed Minhaj

Title:

Exploiting on-chip memory concurrency in 3d manycore architectures

dc.contributor.advisor	Yalamanchili, Sudhakar
dc.contributor.author	Hassan, Syed Minhaj
dc.contributor.committeeMember	Mukhopadhyay, Saibal
dc.contributor.committeeMember	Krishna, Tushar
dc.contributor.committeeMember	Kim, Hyesoon
dc.contributor.committeeMember	Pande, Santosh
dc.contributor.committeeMember	Vuduc, Richard
dc.contributor.department	Electrical and Computer Engineering
dc.date.accessioned	2017-01-11T14:01:53Z
dc.date.available	2017-01-11T14:01:53Z
dc.date.created	2016-12
dc.date.issued	2016-08-26
dc.date.submitted	December 2016
dc.date.updated	2017-01-11T14:01:54Z
dc.description.abstract	The objective of this thesis is to optimize the uncore of 3D many-core architectures. More specifically, we note that technology trends point to large increases in memory-level concurrency. This in turn affects the design of the multi-core interconnect and organization of the memory hierarchy. The work addresses the need for re-optimization in the presence of this increase in concurrency of the memory system. First, we observe that 2D network latency and inefficient parallelism management in the current 3D designs are the main bottlenecks to fully exploit the potentials of 3D. To that end, we propose an extremely low-latency, low-power, high-radix router and present its various versions for different network typologies and configurations. We also explore optimizations and techniques to reduce the traffic in the network. Second, we propose a reorganization of the memory hierarchy and use simple address space translations to regulate locality, bandwidth and energy trade-offs in highly concurrent 3D memory systems. Third, we analyze the rise in temperature of 3D memories and propose variable-rate per-bank refresh management that exploits variability in temperature to reduce 3D DRAM's refresh power and extend its operating range to higher temperatures.
dc.description.degree	Ph.D.
dc.format.mimetype	application/pdf
dc.identifier.uri	http://hdl.handle.net/1853/56251
dc.language.iso	en_US
dc.publisher	Georgia Institute of Technology
dc.subject	3D memory systems
dc.subject	Network-on-chip
dc.subject	3D system thermal analysis
dc.subject	Memory-level parallelism
dc.subject	DRAM
dc.title	Exploiting on-chip memory concurrency in 3d manycore architectures
dc.type	Text
dc.type.genre	Dissertation
dspace.entity.type	Publication
local.contributor.corporatename	School of Electrical and Computer Engineering
local.contributor.corporatename	College of Engineering
relation.isOrgUnitOfPublication	5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication	7c022d60-21d5-497c-b552-95e489a06569
thesis.degree.level	Doctoral