Title:
POD: A Parallel-On-Die Architecture
POD: A Parallel-On-Die Architecture
| dc.contributor.author | Woo, Dong Hyuk | |
| dc.contributor.author | Fryman, Joshua Bruce | |
| dc.contributor.author | Knies, Allan D. | |
| dc.contributor.author | Eng, Marsha | |
| dc.contributor.author | Lee, Hsien-Hsin Sean | |
| dc.date.accessioned | 2008-02-22T20:17:10Z | |
| dc.date.available | 2008-02-22T20:17:10Z | |
| dc.date.issued | 2007-05 | |
| dc.description.abstract | As power constraints, complexity and design verification cost make it difficult to improve single-stream performance, parallel computing paradigm is taking a place amongst mainstream high-volume architectures. Most current commercial designs focus on MIMD-style CMPs built with rather complex single cores. While such designs provide a degree of generality, they may not be the most efficient way to build processors for applications with inherently scalable parallelism. These designs have been proven to work well for certain classes of applications such as transaction processing, but they have driven the development of new languages and complex architectural features. Instead of building MIMD-CMPs for all workloads, we propose an alternative parallel on-die many-core architecture called POD based on a large SIMD PE array. POD helps to address the key challenges of on-chip communication bandwidth, area limitations, and energy consumed by routers by factoring out features necessary for MIMD machines and focusing on architectures that match many scalable workloads. In this paper, we evaluate and quantify the advantages of the POD architecture based its ISA on a commercially relevant CISC architecture and show that it can be as efficient as more specialized array processors based on one-off ISAs. Our single-chip POD is capable of best-in-class scalar performance up to 1.5 TFLOPS of single-precision floating-point arithmetic. Our experimental results show that in some application domains, our architecture can achieve nearly linear speedup on a large number of SIMD PEs, and this speedup is much bigger than the maximum speedup that MIMD-CMPs on the same die size can achieve. Furthermore, owing to synchronized computation and communication, it shows that POD can efficiently suppress energy consumption on the novel communication method in our interconnection network. | en_US |
| dc.identifier.uri | http://hdl.handle.net/1853/20069 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.relation.ispartofseries | CERCS; GIT-CERCS-07-09 | en_US |
| dc.subject | Communication | en_US |
| dc.subject | Cores | en_US |
| dc.subject | Parallel on-die | en_US |
| dc.subject | Processors | en_US |
| dc.subject | Programming | en_US |
| dc.title | POD: A Parallel-On-Die Architecture | en_US |
| dc.type | Text | |
| dc.type.genre | Technical Report | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | Center for Experimental Research in Computer Systems | |
| local.relation.ispartofseries | CERCS Technical Report Series | |
| relation.isOrgUnitOfPublication | 1dd858c0-be27-47fd-873d-208407cf0794 | |
| relation.isSeriesOfPublication | bc21f6b3-4b86-4b92-8b66-d65d59e12c54 |