Title:
Pareto Points in SRAM Design Using the Sleepy Stack Approach

dc.contributor.author Park, Jun Cheol en_US
dc.contributor.author Mooney, Vincent John, III
dc.date.accessioned 2005-06-17T17:34:50Z
dc.date.available 2005-06-17T17:34:50Z
dc.date.issued 2005 en_US
dc.description.abstract Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for SRAM which occupies large transistor count in most state-of-the-art chip designs. We propose a novel ultra-low leakage SRAM design which we call "sleepy stack SRAM." Unlike many other previous approaches, sleepy stack SRAM can retain logic state during sleep mode, which is crucial for a memory element. Compared to the best alternative we could find, a 6T SRAM cell with high-V[subscript th] transistors, the sleepy stack SRAM cell with 1.5xV[subscript th] at 110-degree C achieves more than 5X leakage power reduction at a cost of 31% delay increase and 113% area increase. Alternatively, by widening wordline pass transistors, the sleepy stack SRAM cell can match the delay of the high-V[subscript th] 6T SRAM and still achieve 2.5X leakage power reduction at a cost of a 139% area penalty. en_US
dc.format.extent 198992 bytes
dc.format.mimetype application/pdf
dc.identifier.uri http://hdl.handle.net/1853/6482
dc.language.iso en_US
dc.publisher Georgia Institute of Technology en_US
dc.relation.ispartofseries CC Technical Report; GIT-CC-05-06 en_US
dc.subject Metal oxide semiconductors, Complementary
dc.subject Leakage power consumption
dc.subject Sleepy stack SRAM cell
dc.subject Pareto points
dc.title Pareto Points in SRAM Design Using the Sleepy Stack Approach en_US
dc.type Text
dc.type.genre Technical Report
dspace.entity.type Publication
local.contributor.author Mooney, Vincent John, III
local.contributor.corporatename College of Computing
local.relation.ispartofseries College of Computing Technical Report Series
relation.isAuthorOfPublication 1068070d-f7e9-4b9c-9be6-72023d13e2a1
relation.isOrgUnitOfPublication c8892b3c-8db6-4b7b-a33a-1b67f7db2021
relation.isSeriesOfPublication 35c9e8fc-dd67-4201-b1d5-016381ef65b8
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