Lattice reduction for MIMO detection: from theoretical analysis to hardware realization

dc.contributor.advisor Anderson, David V.
dc.contributor.author Gestner, Brian Joseph en_US
dc.contributor.committeeMember Barry, John
dc.contributor.committeeMember Santosh Pande
dc.contributor.committeeMember Yalamanchili, Sudhakar
dc.contributor.committeeMember Xiaoli Ma
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2011-07-06T16:48:54Z
dc.date.available 2011-07-06T16:48:54Z
dc.date.issued 2011-04-04 en_US
dc.description.abstract The objective of the dissertation research is to understand the complex interaction between the algorithm and hardware aspects of symbol detection that is enhanced by lattice reduction (LR) preprocessing for wireless MIMO communication systems. The motivation for this work stems from the need to improve the bit-error-rate performance of conventional, low-complexity detectors while simultaneously exhibiting considerably reduced complexity when compared to the optimal method, maximum likelihood detection. Specifically, we first develop an understanding of the complex Lenstra-Lenstra-Lovász (CLLL) LR algorithm from a hardware perspective. This understanding leads to both algorithm modifications that reduce the required complexity and hardware architectures that are specifically optimized for the CLLL algorithm. Finally, we integrate this knowledge with an understanding of LR-aided MIMO symbol detection in a highly-correlated wireless environment, resulting in a joint LR/symbol detection algorithm that maps seamlessly to hardware. Hence, this dissertation forms the foundation for the adoption of lattice reduction algorithms in practical, high-throughput wireless MIMO communications systems. en_US
dc.description.degree Ph.D. en_US
dc.identifier.uri http://hdl.handle.net/1853/39591
dc.publisher Georgia Institute of Technology en_US
dc.subject MIMO en_US
dc.subject Wireless en_US
dc.subject Lattice reduction en_US
dc.subject VLSI en_US
dc.subject Hardware en_US
dc.subject FPGA en_US
dc.subject.lcsh MIMO systems
dc.subject.lcsh Wireless communication systems
dc.subject.lcsh Algorithms
dc.title Lattice reduction for MIMO detection: from theoretical analysis to hardware realization en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Anderson, David V.
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
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