Title:
Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints
| dc.contributor.advisor | Wills, D. Scott | |
| dc.contributor.author | Lacy, William Stephen | en_US |
| dc.contributor.department | Electrical and computer engineering | en_US |
| dc.contributor.department | Electric engineering | en_US |
| dc.date.accessioned | 2007-05-31T19:22:39Z | |
| dc.date.available | 2007-05-31T19:22:39Z | |
| dc.date.issued | 1996-12 | en_US |
| dc.description.degree | Ph.D. | en_US |
| dc.identifier.bibid | 444122 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1853/14690 | |
| dc.publisher | Georgia Institute of Technology | en_US |
| dc.rights | Access restricted to authorized Georgia Tech users only. | en_US |
| dc.subject.lcsh | Pattern recognition systems | en_US |
| dc.subject.lcsh | Parallel processing (Electronic computers) | en_US |
| dc.subject.lcsh | Integrated circuits Very large scale integration | en_US |
| dc.title | Design issues for interconnection networks in massively parallel processing systems under advanced VLSI and packaging constraints | en_US |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 |
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