Title:
Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts

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dc.contributor.advisor Lim, Sung Kyu
dc.contributor.author Athikulwongse, Krit en_US
dc.contributor.committeeMember Bakir, Muhannad
dc.contributor.committeeMember Kim, Hyesoon
dc.contributor.committeeMember Mukhopadhyay, Saibal
dc.contributor.committeeMember Swaminathan, Madhavan
dc.contributor.department Electrical and Computer Engineering en_US
dc.date.accessioned 2013-01-17T21:04:45Z
dc.date.available 2013-01-17T21:04:45Z
dc.date.issued 2012-08-17 en_US
dc.description.abstract The objective of this research is to explore the feasibility of addressing the major performance and reliability problems or issues, such as wirelength, stress-induced carrier mobility variation, temperature, and quality trade-offs, found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation in TSV-based 3D ICs is examined. In the third work, temperature inside TSV-based 3D ICs is investigated. In the final work, the quality trade-offs of TSV-based 3D-IC designs are explored. In the first work, a force-directed, 3D, and gate-level placement algorithm that efficiently handles TSVs is developed. The experiments based on synthesized benchmarks indicate that the developed algorithm helps generate GDSII layouts of 3D-IC designs that are optimized in terms of wirelength. In addition, the impact of TSVs on other physical aspects of 3D-IC designs is also studied by analyzing the GDSII layouts. In the second work, the model for carrier mobility variation caused by TSV and STI stresses is developed as well as the timing analysis flow considering the stresses. The impact of TSV and STI stresses on carrier mobility variation and performance of 3D ICs is studied. Furthermore, a TSV-stress-driven, force-directed, and 3D placement algorithm is developed. It exploits carrier mobility variation, caused by stress around TSVs after fabrication, to improve the timing and area objectives during placement. In addition, the impact of keep-out zone (KOZ) around TSVs on stress, carrier mobility variation, area, wirelength, and performance of 3D ICs is studied. In the third work, two temperature-aware global placement algorithms are developed. They exploit die-to-die thermal coupling in 3D ICs to improve temperature during placement. In addition, a framework used to evaluate the results from temperature-aware global placements is developed. The main component of the framework is a GDSII-level thermal analysis that considers all structures inside a TSV-based 3D IC while computing temperature. The developed placers are compared with several state-of-the-art placers published in recent literature. The experimental results indicate that the developed algorithms help improve the temperature of 3D ICs effectively. In the final work, three block-level design styles for TSV-based die-to-wafer bonded 3D ICs are discussed. Several 3D-IC layouts in the three styles are manually designed. The main difference among these layouts is the position of TSVs. Finally, the area, wirelength, timing, power, temperature, and mechanical stress of all layouts are compared to explore the trade-offs of layout quality. en_US
dc.description.degree PhD en_US
dc.identifier.uri http://hdl.handle.net/1853/45783
dc.publisher Georgia Institute of Technology en_US
dc.subject TSV en_US
dc.subject 3D ICs en_US
dc.subject Placement en_US
dc.subject.lcsh Three-dimensional integrated circuits
dc.subject.lcsh Integrated circuits
dc.subject.lcsh Integrated circuits Design and construction
dc.title Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts en_US
dc.type Text
dc.type.genre Dissertation
dspace.entity.type Publication
local.contributor.advisor Lim, Sung Kyu
local.contributor.corporatename School of Electrical and Computer Engineering
local.contributor.corporatename College of Engineering
relation.isAdvisorOfPublication 31bc3e86-9942-4b3f-aeae-783bb95052ff
relation.isOrgUnitOfPublication 5b7adef2-447c-4270-b9fc-846bd76f80f2
relation.isOrgUnitOfPublication 7c022d60-21d5-497c-b552-95e489a06569
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