Title:
Intelligent cache management for heterogeneous memory systems
Intelligent cache management for heterogeneous memory systems
| dc.contributor.advisor | Qureshi, Moinuddin K. | |
| dc.contributor.author | Young, Vinson | |
| dc.contributor.committeeMember | Kim, Hyesoon | |
| dc.contributor.committeeMember | Jaleel, Aamer | |
| dc.contributor.committeeMember | Prvulovic, Milos | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.date.accessioned | 2019-08-21T13:51:32Z | |
| dc.date.available | 2019-08-21T13:51:32Z | |
| dc.date.created | 2019-08 | |
| dc.date.issued | 2019-05-21 | |
| dc.date.submitted | August 2019 | |
| dc.date.updated | 2019-08-21T13:51:32Z | |
| dc.description.abstract | DRAM caches are important for enabling effective heterogeneous memory systems that can transparently provide the bandwidth of high-bandwidth memories and the capacity of high-capacity memories. This dissertation investigates enabling intelligent cache management for tag-inside-cacheline DRAM cache designs. Such a DRAM cache uses a direct-mapped design, co-locates the tag and data within the DRAM array, and streams out the tag and the data concurrently on an access. The direct-mapped design has been shown to be effective for enabling low latency and bandwidth-efficient tag access. However, such a direct-mapped design can have lower hit-rate and high bandwidth cost to confirm misses. This dissertation investigates simple architectural techniques to improve the hit-rate and bandwidth consumption of such DRAM caches by enabling associativity, replacement policies, and reduced miss probes at low bandwidth cost to improve the performance of heterogeneous memory systems. | |
| dc.description.degree | Ph.D. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/1853/61710 | |
| dc.language.iso | en_US | |
| dc.publisher | Georgia Institute of Technology | |
| dc.subject | Non-volatile memory | |
| dc.subject | 3D-XPoint | |
| dc.subject | Stacked DRAM | |
| dc.subject | HBM | |
| dc.subject | Hybrid memory | |
| dc.subject | DRAM cache | |
| dc.subject | Associativity | |
| dc.subject | Compression | |
| dc.subject | Way prediction | |
| dc.subject | Replacement policy | |
| dc.title | Intelligent cache management for heterogeneous memory systems | |
| dc.type | Text | |
| dc.type.genre | Dissertation | |
| dspace.entity.type | Publication | |
| local.contributor.advisor | Qureshi, Moinuddin K. | |
| local.contributor.corporatename | School of Electrical and Computer Engineering | |
| local.contributor.corporatename | College of Engineering | |
| relation.isAdvisorOfPublication | dc173edd-5db7-4644-b1f6-37fc65b2c9af | |
| relation.isOrgUnitOfPublication | 5b7adef2-447c-4270-b9fc-846bd76f80f2 | |
| relation.isOrgUnitOfPublication | 7c022d60-21d5-497c-b552-95e489a06569 | |
| thesis.degree.level | Doctoral |