Title:
Distributed Instruction Queue

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dc.contributor.patentcreator Chamdani, Joseph I.
dc.contributor.patentcreator Alford, Cecil O.
dc.date.accessioned 2017-05-12T14:27:33Z
dc.date.available 2017-05-12T14:27:33Z
dc.date.filed 6/12/1995
dc.date.issued 8/29/2000
dc.description.abstract A distributed instruction queue (DIQ) in a superscalar microprocessor supports multi-instruction issue, decoupled data flow scheduling, out-of-order execution, register renaming, multi-level speculative execution, and precise interrupts. The DIQ provides distributed instruction shelving without storing register values, operand value copying, and result value forwarding, and supports in-order issue as well as out-of-order issue within its functional unit. The DIQ allows a reduction in the number of global wires and replacement with private-local wires in the processor. The DIQ's number of global wires remains the same as the number of DIQ entries and data size increases. The DIQ maintains maximum machine parallelism and the actual performance of the microprocessor using the DIQ is better due to reduced cycle time or more operations executed per cycle.
dc.description.assignee Georgia Tech Research Corp.
dc.identifier.cpc G06F9/3836
dc.identifier.cpc G06F9/3838
dc.identifier.cpc G06F9/384
dc.identifier.patentapplicationnumber 08/489509
dc.identifier.patentnumber 6112019
dc.identifier.uri http://hdl.handle.net/1853/57348
dc.identifier.uspc 712/214
dc.title Distributed Instruction Queue
dc.type Text
dc.type.genre Patent
dspace.entity.type Publication
local.contributor.corporatename Georgia Institute of Technology
local.relation.ispartofseries Georgia Tech Patents
relation.isOrgUnitOfPublication cc30e153-7a64-4ae2-9b1d-5436686785e3
relation.isSeriesOfPublication 0f49c79d-4efb-4bd9-b060-5c7f9191b9da
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